Analog frontend circuit and signal filtering method for photoplethysmography

An analog frontend circuit for photoplethysmography includes a current control circuit and a monitoring circuit both coupled with a first node, and also includes a reading circuit coupled with the first node through the monitoring circuit. The current control circuit generates a first sub-current which is part of an input current flowing to the first node. In a tracking period, the monitoring circuit controls the current control circuit to determine magnitude of the first sub-current to control a voltage of the first node to track a reference voltage. In a sensing period after the tracking period, the monitoring circuit controls the current control circuit to keep the first sub-current determined in the tracking period. After the first sub-current is kept, the monitoring circuit provides a second sub-current which is part of the input current, and the reading circuit converts the second sub-current to an output voltage.

1. 11. An analog frontend circuit for photoplethysmography, comprising: a first current control circuit, coupled with a first node, and configured to generate a first sub-current, wherein the first sub-current is part of an input current flowing to the first node; a monitoring circuit, coupled with the first node, and configured to receive a reference voltage, wherein in a tracking period, the monitoring circuit is configured to control the first current control circuit to determine a magnitude of the first sub-current, in order to control a voltage of the first node to track the reference voltage; and a reading circuit, coupled with the first node through the monitoring circuit, wherein in a sensing period after the tracking period, the monitoring circuit is configured to control the first current control circuit to keep the first sub-current to have the magnitude of the first sub-current determined in the tracking period, wherein after the first sub-current is kept, the monitoring circuit is configured to transmit a second sub-current from the first node to the reading circuit so that the reading circuit is configured to convert the second sub-current to an output voltage, wherein the second sub-current is part of the input current.
2. 22. The analog frontend circuit of claim 1, wherein the monitoring circuit comprises: an amplifier, comprising a first input terminal, a second input terminal and an output terminal, wherein the second input terminal of the amplifier is coupled with the reading circuit; a sample-and-hold circuit, coupled with the output terminal of the amplifier and the first current control circuit, configured to sample an output of the amplifier, wherein the sample-and-hold circuit is configured to output the sampled output of the amplifier to control the first current control circuit to determine the magnitude of the first sub-current; and a switch array, coupled with the first node, the first input terminal and the second input terminal of the amplifier, configured to receive the reference voltage, wherein in the tracking period, the switch array is configure to respectively provide the second sub-current and the reference voltage to the first input terminal and the second input terminal of the amplifier, and wherein in the sensing period, the switch array is configure to respectively provide the second sub-current and the reference voltage to the second input terminal and the first input terminal of the amplifier.
3. 33. The analog frontend circuit of claim 2, wherein the sample-and-hold circuit comprises: a sampling capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the sampling capacitor is coupled with the first current control circuit, and the second terminal of the sampling capacitor is configured to receive a first operation voltage; and a sampling switch, coupled between the output terminal of the amplifier and the first terminal of the sampling capacitor, wherein the sampling switch is conducted in the tracking period and is switched off in the sensing period.

BACKGROUND
Technical Field
The present disclosure relates to photoplethysmography. More particularly, the present disclosure relates to an analog front end circuit and a signal filtering method for photoplethysmography.
Description of Related Art
Photoplethysmography (PPG) is an optical method to measure heart rate and blood oxygen saturation. In PPG, light-emitting diodes (LEDs) emit light toward skin of a user, and the light reflect by blood and human tissue of the user is measured and transformed to a current signal by an optical sensor. However, a DC component of the current signal may be dominated by slowly-changed ambient light (e.g., light from a light bulb), and an AC component of the current signal may be dominated by fast-changed ambient light (e.g., light change caused by activities of the user). To improve accuracy of PPG, the components of the current signal that are caused by the ambient light should be filtered out, so as to facilitate analysis of a back-end circuit to the AC component and DC component of the current signal that are related to the blood and the human tissue.
SUMMARY
The present disclosure provides an analog frontend circuit for photoplethysmography, which includes a first current control circuit, a monitoring circuit and a reading circuit. The first current control circuit is coupled with a first node, and configured to generate a first sub-current. The first sub-current is part of an input current flowing to the first node. The monitoring circuit is coupled with the first node, and is configured to receive a reference voltage. In a tracking period, the monitoring circuit is configured to control the first current control circuit to determine magnitude of the first sub-current, in order to control a voltage of the first node to track the reference voltage. The reading circuit is coupled with the first node through the monitoring circuit. In a sensing period after the tracking period, the monitoring circuit is configured to control the first current control circuit to keep the first sub-current to have the magnitude of the first sub-current determined in the tracking period. After the first sub-current is kept, the monitoring circuit is configured to transmit a second sub-current from the first node to the reading circuit so that the reading circuit is configured to convert the second sub-current to an output voltage. The second sub-current is part of the input current.
The present disclosure provides a signal filtering method for photoplethysmography. The signal filtering method includes the following steps: monitoring, in a tracking period and by a monitoring circuit, a voltage of a first node and a reference voltage, wherein an input current flows to the first node; controlling, in the tracking period and by the monitoring circuit, a first current control circuit coupled to the first node to determine magnitude of a first sub-current, in which the first sub-current is part of the input current and generated by the first current control circuit; in a sensing period after the tracking period, controlling, by the monitoring circuit, the first current control circuit to keep the first sub-current to have the magnitude of the first sub-current determined in the tracking period; and after the first sub-current is kept, converting, by a reading circuit coupled with the first node through the monitoring circuit, a second sub-current transmitted from the first node through the monitoring circuit to the reading circuit to an output voltage, in which the second sub-current is part of the input current.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified functional block diagram of an analog frontend circuit for photoplethysmography, according to one embodiment of the present disclosure.
FIG. 2 is a schematic diagram of the input current according to one embodiment of the present disclosure.
FIG. 3 is a flowchart of a signal filtering method for photoplethysmography.
FIG. 4 is a schematic diagram of a first current control circuit according to one embodiment of the present disclosure.
FIG. 5 is a schematic diagram of a reading circuit according to one embodiment of the present disclosure.
FIG. 6 is a schematic diagram of a reading circuit according to one embodiment of the present disclosure.
FIG. 7 is a waveform schematic diagram of the reading circuit according to one embodiment of the present disclosure.
FIG. 8 is a waveform schematic diagram of the reading circuit according to one embodiment of the present disclosure.
FIG. 9 is a schematic diagram of a second current control circuit according to one embodiment of the present disclosure.



DETAILED DESCRIPTION
Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIG. 1 is a simplified functional block diagram of an analog frontend circuit 100 for photoplethysmography (PPG), according to one embodiment of the present disclosure. The analog frontend circuit 100 comprises a first current control circuit 110, a monitoring circuit 120, a reading circuit 130 and a second current control circuit 140. The analog frontend circuit 100 is configured to convert an input current I_in to an output voltage Vout, in which the input current I_in is generated by an optical sensor (not shown) through transforming absorbed light to a current signal. An analog-to digital converter (ADC) 101 is configured to convert the output voltage Vout, where a digital signal processor (DSP) 103 is configured to receive and analyze an output of the ADC 101 to obtain physiological information PI (e.g., heart rate, blood oxygen saturation, etc.,) of a user. The DSP 103 is further configured to realize a feedback control to the analog frontend circuit 100 based on the analysis to the output of the ADC 101, which will be described in greater detail in the following paragraphs.
Reference is made to FIG. 2, in which FIG. 2 is a schematic diagram of the input current I_in according to one embodiment of the present disclosure. When a light source (e.g., an LED, not shown in FIG. 1) of PPG is disabled and no light is reflected from the user, the input current I_in comprises an ambient AC component Iac_amb and an ambient DC component Idc_amb that respectively caused by fast-changed ambient light and slowly-changed ambient light absorbed by the optical sensor. In addition, when the light source of PPG is enabled and there is light reflected by blood and/or tissue of the user to the optical sensor, except for the ambient AC component Iac_amb and the ambient DC component Idc_amb, the input current I_in further comprises a reflected AC component Iac_rfl and a reflected DC component Idc_rfl. The reflected AC component Iac_rfl may be caused by the light reflected by the blood, subcutis or bones of the user that are dynamically changed (i.e., time-variant). The reflected DC component Idc_rfl may be caused by the light reflected by the blood, subcutis or bones of the user that remain static (i.e., time-invariant).
Reference is made to FIG. 1 and FIG. 3, in which FIG. 3 is a flowchart of a signal filtering method 300 for PPG. In step S310 conducted in a tracking period, the monitoring circuit 120, which is coupled with a first node N1 and is configured to receive a reference voltage Vref, monitors a voltage of the first node N1 and the reference voltage Vref, where the input current I_in flows to the first node N1. The tracking period is a period where the light source of PPG is disabled, and therefore, the input current I_in in the tracking period comprises only the ambient AC component Iac_amb and the ambient DC component Idc_amb.
In step S320 conducted in the tracking period, the monitoring circuit 120 controls the first current control circuit 110 to determine a magnitude of a first sub-current I_sub1, in order to configure the voltage of the first node N1 to track the reference voltage Vref. The first current control circuit 110 is coupled with the first node N1, and is configured to generate the first sub-current I_sub1, where the first sub-current I_sub1 is part of the input current I_in flowing to the first node N1. In specific, in the tracking period, the monitoring circuit 120 sets the voltage of the first node N1 to the reference voltage Vref by virtual short effect of an amplifier 122, and uses a control signal Seao to dynamically control the first current control circuit 110 to drain most of the input current I_in as the first sub-current I_sub1, where the control signal Seao is generated by the monitoring circuit 120 according to the voltage of the first node N1 and the reference voltage Vref. As a result, a second sub-current I_sub2, which flows from the first node N1 to the monitoring circuit 120 and is part of the input current I_in, is small and hardly changes the voltage of the first node N1 so that the voltage of the first node N1 remains at the reference voltage Vref. Alternatively stated, the first current control circuit 110 and the monitoring circuit 120 form a tracking loop that continuously tracks the change of the ambient light. The change of the ambient light causes the monitor circuit 120 to control the first current control circuit 110 to adjust the first sub-current I_sub1, so that the first sub-current I_sub1 varies with the ambient light. Thus, the first sub-current I_sub1 is approximated to a sum of the ambient AC component Iac_amb and the ambient DC component Idc_amb, and the second sub-current I_sub2 is substantially zero.
In step S330 conducted in a sensing period after the tracking period, the monitoring circuit 120 controls the first current control circuit 110 to keep the first sub-current I_sub1 to have the magnitude determined in the tracking period. The sensing period is a period where the light source of PPG is enabled, and therefore, the input current I_in in the sensing period comprises the ambient AC component Iac_amb, the ambient DC component Idc_amb, the reflected AC component Iac_rfl and the reflected DC component Idc_rfl.
In step S340 conducted after the first sub-current I_sub1 is kept at the fixed magnitude, the reading circuit 130 is configured to convert the second sub-current I_sub2 to the output voltage Vout. The reading circuit 130 is coupled with the first node N1 through the monitoring circuit 120, and the second sub-current I_sub2 is part of the input current I_in. The second sub-current I_sub2 is transmitted from the first node N1 through (e.g., by) the monitoring circuit 120 to the reading circuit 130.
In step S350, the second current control circuit 140 coupled with the first node N1 is configured to generate a third sub-current I_sub3 in the sensing period. The second current control circuit 140 is further configured to determine a magnitude of the third sub-current I_sub3 according to a magnitude of the second sub-current I_sub2 in a former sensing period, which will be described in greater detail in the following paragraphs. The third sub-current I_sub3 is configured by the feedback control of the DSP 103 to approximate to the reflected DC component Idc_rfl, and is part of the input current I_in.
Accordingly, the ambient DC component Idc_amb is filtered out by the first current control circuit 110 through the first sub-current I_sub1, and the reflected DC component Idc_rfl is filtered out by the second current control circuit 140 through the third sub-current I_sub3. The second sub-current I_sub2 is approximated to the combination of the ambient AC component Iac_amb and the reflected AC component Iac_refl. Since the second sub-current I_sub2 is small, the reading circuit 130 may be implemented as having a large gain (e.g., selecting resistors with large resistance to form a storage array in FIG. 5) when converting the second sub-current I_sub2 to the output voltage Vout, without a risk that the output voltage Vout exceeds a dynamic range of the ADC 101.
The details of step S310 are described below. The monitoring circuit 120 comprises the amplifier 122, a sample-and-hold circuit 124 and a switch array 126 which cooperatively conduct step S310. The amplifier 122 comprises a first input terminal (e.g., a non-inverted input terminal), a second input terminal (e.g., an inverted input terminal, labeled as a second node N2) and an output terminal (labeled as a third node N3). The second input terminal of the amplifier 122 is coupled with the reading circuit 130. In some embodiments, the amplifier 122 may be implemented by using an operational amplifier (OPAMP) or an operational transconductance amplifier (OTA).
The sample-and-hold circuit 124 is coupled with the output terminal of the amplifier 122. The sample-and-hold circuit 124 is configured to sample an output of the amplifier 122 (labeled as the control signal Seao), and further configured to output the sampled output of the amplifier 122 to the first current control circuit 110, so as to control the first current control circuit 110 to determine the magnitude of the first sub-current I_sub1. In specific, the sample-and-hold circuit 124 comprises a sampling switch SW and a sampling capacitor SC. The sampling capacitor SC comprises a first terminal and a second terminal, where the first terminal of the sampling capacitor SC is coupled with the first current control circuit 110, and the second terminal of the sampling capacitor SC is configured to receive a first operation voltage (e.g., the ground voltage). The sampling switch SW is coupled between the output terminal of the amplifier 122 and the first terminal of the sampling capacitor SC. The sampling switch SW is conducted in the tracking period so that the sampling capacitor SC samples the control signal Seao. On other hand, the sampling switch SW is switched off in the sensing period so that the sampling capacitor SC holds the sampled control signal Seao.
The switch array 126 is coupled with the first node, the first input terminal and the second input terminal of the amplifier 122, and is configured to receive the reference voltage Vref. In some embodiments, the switch array 126 may be implemented by using two single-pole double-throw (SPDT) switches. In the tracking period, the switch array 126 is configured to connect the first node N1 to the first input terminal of the amplifier 122 to provide the second sub-current I_sub2 to the first input terminal of the amplifier 122. The switch array 126 is further configured to provide the reference voltage Vref to the second input terminal of the amplifier 122 in the tracking period. Therefore, the amplifier 122 sets the first node N1 to the reference voltage Vref in the tracking period by the virtual short effect between the first input terminal and the second input terminal of the amplifier 122. The control signal Seao reflects divergence between the voltage of the first node N1 and the reference voltage Vref. For example, the control signal Seao may have a high voltage when the voltage of the first node N1 is different from and higher than the reference voltage Vref, and have a low voltage when the voltage of the first node N1 is different from and lower than the reference voltage Vref, but this disclosure is not limited thereto.
Accordingly, step S310 conducted in the tracking period comprises: receiving the second sub-current I_sub2 and the reference voltage Vref by the switch array 126; and transmitting the second sub-current I_sub2 and the reference voltage Vref respectively to the first input terminal and the second input terminal of the amplifier 122.
The details of step S320 are described below. The monitoring circuit 120 and the first current control circuit 110 are configured to cooperatively conduct step S320. The first current control circuit 110 comprises a transistor M1. The transistor M1 comprises a first terminal, a second terminal and a control terminal, and the first sub current I_sub1 flows through the transistor M1. The first terminal of the transistor M1 is coupled with the first node N1. The second terminal of the transistor M1 is configured to receive the first operation voltage (e.g., the ground voltage). The control terminal of the transistor M1 is coupled with the monitoring circuit 120 (i.e., the first terminal of the sampling capacitor CA) to receive the control signal Seao generated by the monitoring circuit 120 according to the voltage of the first node N1 and the reference voltage Vref.
As aforementioned, the sampling switch SW is conducted in the tracking period. Therefore, the sampling capacitor SC samples the output of the amplifier 122 (i.e., the control signal Seao), and outputs the sampled output of the amplifier 122 to the control terminal of the transistor M1, so that the transistor M1 dynamically determines the magnitude of the first sub-current I_sub1 according to the output of the amplifier 122.
Accordingly, step S320 conducted in the tracking period comprises: sampling the output of the amplifier 122 by the sample-and-hold circuit 124 coupled with the output terminal of the amplifier 122 and the first current control circuit 110; and outputting, by the sample-and-hold circuit 124, the sampled output of the amplifier 122 to the first current control circuit 110, so as to control the first current control circuit 110 to determine the magnitude of the first sub-current I_sub1. Viewed from another perspective, the step S320 comprises: generating the control signal Seao by the monitoring circuit 120 according to the voltage of the first node N1 and the reference voltage Vref; and using the transistor M1 of the first current control circuit 110 to determine the magnitude of the first sub-current I_sub1 according to the control signal Seao.
The details of step S330 are described below. In the sensing period after the tracking period, the switch array 126 is configured to connect the first node N1 to the second input terminal of the amplifier 122 to provide the second sub-current I_sub2 to the second input terminal of the amplifier 122, and therefore, the second sub-current I_sub2 is also provided to the reading circuit 130. The switch array 126 is further configured to provide the reference voltage Vref to the first input terminal of the amplifier 122 in the sensing period. In addition, the sampling switch SW of the sample-and-hold circuit 124 is switched off, so that the sampling capacitor SC keeps the output of the amplifier 122 (i.e., the control signal Seao) sampled in the tracking period. As a result, the first terminal of the sampling capacitor SC outputs a fixed voltage to the control terminal of the transistor M1, so as to control the transistor M1 to keep the first sub-current I_sub1 at the magnitude determined in the tracking period.
Accordingly, step S330 conducted in the sensing period comprises: switching off the sampling switch SW of the sample-and-hold circuit 124; and outputting the sampled output of the amplifier 122, by the first terminal of the sampling capacitor SC of the sample-and-hold circuit 124, to the first current control circuit 110 to control the first current control circuit 110 to keep the first sub-current I_sub1 to have the magnitude determined in the tracking period.
Reference is made to FIG. 4, in which FIG. 4 is a schematic diagram of a first current control circuit 400 according to one embodiment of the present disclosure. In some embodiments, the first current control circuit 110 in FIG. 1 may be replaced with the first current control circuit 400 of FIG. 4. The first current control circuit 400 comprises a transistor M1′ and a first current mirror CM1. The transistor M1′ comprises a first terminal, a second terminal and a control terminal. The first terminal of the transistor M1′ is configured to receive a second operation voltage (e.g., a high voltage VDD), and the second operation voltage is higher than the first operation voltage (e.g., the ground voltage). The control terminal of the transistor M1′ is coupled with the monitoring circuit 120 to receive the control signal Seao generated by the monitoring circuit 120 according to the voltage of the first node N1 and the reference voltage Vref. Specifically, the control terminal of the transistor M1′ is coupled with the first terminal of the sampling capacitor SC of the sample-and-hold circuit 124.
The first current mirror CM1 comprises an input terminal and an output terminal. The input terminal of the first current mirror CM1 is coupled with the second terminal of the transistor M1′. The output terminal of the first current mirror CM1 is coupled with the first node N1, and the first sub-current I_sub1 flows through the output terminal of the first current mirror CM1. The output of the amplifier 122 (i.e., the control signal Seao) controls a conduction degree of the transistor M1′, so as to use a current which is generated by the transistor M1′ and flows to the input terminal of the first current mirror CM1 to control the first current mirror CM1 to determine the magnitude of the first sub-current I_sub1.
Accordingly, in the embodiments that the first current control circuit 110 is replaced by the first current control circuit 400, step S320 conducted in the tracking period comprises: generating the control signal Seao by the monitoring circuit 120 according to the voltage of the first node N1 and the reference voltage Vref; receiving the control signal Seao by the control terminal of the transistor M1′ of the first current control circuit 400; and using the first current mirror CM1 of the first current control circuit 400 to determine the magnitude of the first sub-current I_sub1. In the embodiments regarding the first current control circuit 400, steps S310, S330 and S340 are similar to those discussed with the first current control circuit 110, and therefore the detailed descriptions thereof are omitted here.
The details of step S340 are described below. Reference is made to FIG. 5, in which FIG. 5 is a schematic diagram of a reading circuit 500 according to one embodiment of the present disclosure. The reading circuit 500 of FIG. 5 may be used to realize the reading circuit 130 of FIG. 1. The reading circuit 500 comprises a first switching circuit 510, a second switching circuit 520 and a storage array 530. The first switching circuit 510 comprises first switches S1[1]-S1[n] and is coupled between the second node N2 and the storage array 530, where n is a positive integer. The second switching circuit 520 comprises second switches S2[1]-S2[n] and is coupled between the third node N3 and the storage array 530. The storage array 530 comprises resistors R[1]-R[n] coupled in parallel between the first switching circuit 510 and the second switching circuit 520. In specific, first terminals of the resistors R[1]-R[n] are coupled with the second node N2 (i.e., the second input terminal of the amplifier 122) through the first switches S1[1]-S1[n], respectively. Second terminals of the resistors R[1]-R[n] are coupled with the third node N3 (i.e., the output terminal of the amplifier 122) through the second switches S2[1]-S2[n], respectively. That is, the storage array 530 is coupled with the second input terminal of the amplifier 122 through the first switching circuit 510, and is coupled with the output terminal of the amplifier 122 through the second switch circuit 520.
The first switches S1[1]-S1[n] and the second switches S2[1]-S2[n] are switched off in the tracking period, and are conducted in the sensing period. In the sensing period, when the second sub-current I_sub2 flows from the second node N2 through the resistors R[1]-R[n] to the third node N3, the output voltage Vout is generated at the third node N3 (i.e., the output terminal of the amplifier 122). In some embodiments, the reading circuit 500 further comprises a reset circuit 540, where the reset circuit 540 may short the second node N2 to the third node N3 to reset the output voltage Vout.
In some embodiments, one or more of the resistors R[1]-R[n] may be replaced with one or more capacitors, respectively, to realize an integrator. In some embodiments, the first switches S1[1]-S1[n] or the second switches S2[1]-S2[n] may be omitted, that is, the reading circuit 130 may comprise at least one switching circuit and the storage array 530, where the at least one switching circuit and the storage array 530 are coupled between the second input terminal of the amplifier 122 and the output terminal of the amplifier 122, and the at least one switching circuit is switched off in the tracking period and conducted in the sensing period. Accordingly, in the embodiments regarding FIG. 5, step S340 conducted in the sensing period and comprises: receiving the second sub-current I_sub2 by the storage array 530 of the reading circuit 500; and in response to the second sub-current I_sub2 flowing through the storage array 530 and the at least one switching circuit, generating the output voltage Vout at the output terminal of the amplifier 122.
Reference is made to FIG. 6, in which FIG. 6 is a schematic diagram of a reading circuit 600 according to one embodiment of the present disclosure. The reading circuit 600 comprises a first switching circuit 610, a second switching circuit 620, and a storage array 630. The first switching circuit 610 comprises first switches S[1]-S[4] and is coupled between the second node N2 and the storage array 630. The second switch circuit comprises second switches S2[1]-S2[4] and is coupled between the third node N3 and the storage array 630. The storage array 630 comprises a first capacitor C[1] and a second capacitor C[2]. Two terminals of the first capacitor C[1] are coupled with the second node N2 (i.e., the second input terminal of the amplifier 122) through the first switches S[1] and S[2], respectively, and are coupled with the third node N3 (i.e., the output terminal of the amplifier 122) through the second switches S2[1] and S2[2], respectively. Two terminals of the second capacitor C[2] are coupled with the second node N2 (i.e., the second input terminal of the amplifier 122) through the first switches S[3] and S[4], respectively, and are coupled with the third node N3 (i.e., the output terminal of the amplifier 122) through the second switches S2[3] and S2[4], respectively.
Reference is made to FIG. 6, FIG. 7 and FIG. 8, in which FIGS. 7 and 8 are waveform schematic diagrams of the reading circuit 600 according to some embodiments of the present disclosure. In FIGS. 7 and 8, a high level of the waveform represents that the corresponding component is conducted or enabled, and a low level of the waveform represents that the corresponding component is switched off or disabled. The embodiment of FIG. 7 is discussed first. In the sensing period of FIG. 7, the light source of the PPG is enabled, and the first switching circuit 610 and the second switching circuit 620 form a first circuit topology to transmit the second sub-current I_sub2 to the first capacitor C[1] and the second capacitor C[2]. In addition, the first circuit topology configures the first capacitor C[1] and the second capacitor C[2] to be coupled in parallel between the second node N2 (i.e., the second input terminal of the amplifier 122) and the third node N3 (i.e., the output terminal of the amplifier 122). In one embodiment, the first circuit topology may be realized by conducting the first switches S1[1] and S1[4] and the second switches S2[2] and S2[3] and switching off the other switches. As a result, the ambient AC component Iac_amb and the reflected AC component Iac_rfl are stored in both the first capacitor C[1] and the second capacitor C[2].
In a holding period after the sensing period of FIG. 7 (i.e., after the first circuit topology is formed), the light source of the PPG is disabled, and the first switching circuit 610 and the second switching circuit 620 form a second circuit topology to transmit the second sub-current I_sub2 to the second capacitor C[2]. In one embodiment, the second circuit topology may be realized by conducting the first switch S1[4] and the second switch S2[3] and switching off the other switches. In some embodiments, the second switch S2[2] may remain conducted in the holding period. As a result, the information stored in the second capacitor C[2] is updated to including only the ambient AC component Iac_amb.
In an output period after the holding period of FIG. 7 (i.e., after the second circuit topology is formed), the first switching circuit 610 and the second switching circuit 620 form a third circuit topology to conduct charge sharing between the first capacitor C[1] and the second capacitor C[2] to cancel the ambient AC component Iac_amb stored in the first capacitor C[1]. In specific, a positive terminal (e.g., the first terminal) and a negative terminal (e.g., the second terminal) of the first capacitor C[1] are respectively coupled to a negative terminal (e.g., the first terminal) and a positive terminal (e.g., the second terminal) of the second capacitor C[2]. In some embodiments, the third circuit topology may be realized by conducting the first switches S1[1] and S1[3] and the second switches S2[2] and S2[4] and switching off the other switches. As a result, the output voltage Vout is generated in the output period and comprises only the reflected AC component Iac_rfl representing the heart rate, the blood oxygen saturation, etc. It will be understood that the number of capacitors of the storage array 630 is not intended to limit the scope of the present disclosure but is instead provided as an exemplary embodiment, where the storage array 630 may comprise more than two capacitors for performing the charging sharing to cancel the ambient AC component Iac_amb.
Reference is made to FIG. 8, in the sensing period of FIG. 8, the first switching circuit 610 and the second switching circuit 620 form a different first circuit topology to transmit the second sub-current I_sub2 to the first capacitor C[1] but not to the second capacitor C[2]. Other operation periods of FIG. 8 are respectively similar to the corresponding periods discussed with reference to FIG. 7, and therefore the detailed descriptions thereof are omitted here.
Accordingly, step S340 regarding the embodiments of FIG. 6 and FIG. 7 is conducted in the sending period through the output period and comprises: in the sensing period, controlling the first switching circuit 610 and the second switching circuit 620 of the reading circuit 130 to form the first circuit topology, in order to transmit the second sub-current I_sub2 to the first capacitor C[1] and the second capacitor C[2] of the reading circuit 130 and to configure the first capacitor C[1] and the second capacitor C[2] to be coupled in parallel between the second input terminal of the amplifier 122 and the output terminal of the amplifier 122; after the first circuit topology is formed, controlling the first switching circuit 610 and the second switching circuit 620 to form the second circuit topology to transmit the second sub-current I_sub2 to the second capacitor C[2]; and after the second circuit topology is formed, controlling the first switching circuit 610 and the second switching circuit 620 to form the third circuit topology to conduct charge sharing between the first capacitor C[1] and the second capacitor C[2].
In addition, step S340 regarding the embodiments of FIG. 6 and FIG. 8 is conducted in the sending period through the output period and comprises: in the sensing period, controlling the first switching circuit 610 and the second switching circuit 620 of the reading circuit 130 to form the first circuit topology, in order to transmit the second sub-current I_sub2 to the first capacitor C[1] of the reading circuit 130; after the first circuit topology is formed, controlling the first switching circuit 610 and the second switching circuit 620 to form the second circuit topology to transmit the second sub-current I_sub2 to the second capacitor C[2]; and after the second circuit topology is formed, controlling the first switching circuit 610 and the second switching circuit 620 to form the third circuit topology to conduct charge sharing between the first capacitor C[1] and the second capacitor C[2].
The details of step S350 are described below. Reference is made to FIG. 9, in which FIG. 9 is a schematic diagram of a second current control circuit 900 according to one embodiment of the present disclosure. The second current control circuit 900 is coupled with the first node N1, and may be used to realize the second current control circuit 140 in FIG. 1. The second current control circuit 900 comprises a second current mirror 910, a switch array 920 and an enablement switch 930. The second current mirror 910 comprises an input terminal and at least one output terminal, where the input terminal of the second current mirror 910 is configured receive a reference current I_ref. The enablement switch 930 comprises a first terminal and a second terminal, where the first terminal of the enablement switch 930 is coupled with the first node to receive the third sub-current I_sub3. The enablement switch 930 is configured to be conducted in the sensing period.
The switch array 920 is coupled between the second terminal of the enablement switch 930 and the at least one output terminal of the second current mirror 910. In specific, the switch array 920 comprises at least one switch (e.g., switches 922[1]-922[k], in which k is a positive integer) which is respectively coupled with the at least one output terminal of the second current mirror 910. The switches 922[1]-922[k] are respectively controlled by bits Sca[1]-Sca[k] of a calibration signal. In some embodiments, the calibration signal is generated and adjusted by the DSP 103 of FIG. 1 in the current sensing period, according to magnitude of the second sub-current in a former sensing period.
In specific, when the third sub-current I_sub3 is different from the reflected DC component Idc_rfl, the second sub-current I_sub2 in the former sensing period includes part of the reflected DC component Idc_rfl which is not filtered out by the third sub-current I_sub3 (hereinafter referred to as a redundant DC component). The DSP 103 is configured to detect a magnitude of the redundant DC component from the output of the ADC, and configured to adjust the bits Sca[1]-Sca[k] according to the magnitude of the redundant DC component, so as to configure the third sub-current I_sub3 generated by the second current control circuit 900 to approach to the reflected DC component Idc_rfl.
Accordingly, step S350 comprises: determining, in the sensing period and by the second current control circuit 900 (or the second current control circuit 140 of FIG. 1), a magnitude of the third sub-current I_sub3 according to a magnitude of the second sub-current I_sub2 in the former sensing period, in which the third sub-current I_sub3 is part of the input current I_in.
It will be understood that the signal filtering method 300 discussed above may include greater or fewer operations than illustrated in the flowchart of FIG. 3 and the operations may be performed in any order, as appropriate. For example, steps S301 and S302 may be performed simultaneously. As another example, the steps S303, S304 and S305 may be performed simultaneously.
In some embodiments, the N-type and P-type transistors in FIG. 1, FIG. 4 and FIG. 9 may be replaced with the P-type and N-type transistors, respectively. In addition, the first operation voltage which is denoted by the ground symbol in FIG. 1 may be replaced with a high voltage, and the second operation voltage which is denoted by the high voltage in FIG. 1 may be replaced by a low voltage. In this situation, the input current I_in, the first sub-current I_sub1, the second sub-current I_sub2 and the third sub-current I_sub3 have directions respectively opposite to the directions thereof shown in FIG. 1.
Certain terms are used in the specification and the claims to refer to specific components. However, those of ordinary skill in the art would understand that the same components may be referred to by different terms. The specification and claims do not use the differences in terms as a way to distinguish components, but the differences in functions of the components are used as a basis for distinguishing. Furthermore, it should be understood that the term “comprising” used in the specification and claims is open-ended, that is, including but not limited to. In addition, “coupling” herein includes any direct and indirect connection means. Therefore, if it is described that the first component is coupled to the second component, it means that the first component can be directly connected to the second component through electrical connection or signal connections including wireless transmission, optical transmission, and the like, or the first component is indirectly electrically or signally connected to the second component through other component(s) or connection means.
It will be understood that, in the description herein and throughout the claims that follow, the phrase “and/or” includes any and all combinations of one or more of the associated listed items. Unless the context clearly dictates otherwise, the singular terms used herein include plural referents.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.