Balance system to regulate the voltage of the fly capacitor of a three-level buck acting on ramps

A three-level DC-DC converter includes a power-stage with high and low-side transistors, a flying capacitor, and an inductor coupled between an output tap of the power-stage and an output node of the converter. A feedback-divider is coupled in parallel with an output capacitor between the output node and ground and generates a feedback-voltage. A ramp-generator generates a first ramp-signal based on a constant reference-voltage and generates a second ramp-signal based on a difference between a voltage across the flying capacitor and one-half the input-voltage. Control-circuitry generates an error-signal based on a comparison between the feedback-voltage and a reference, generates a first high-side control-signal and a first low-side control-signal for the power-stage, based on a comparison between the first ramp-signal and the error-signal, and generates a second high-side control-signal and a second low-side control-signal for the power-stage, based on a comparison between the second ramp-signal and the error-signal.

1. 11. A DC-DC converter, comprising: a power stage comprising: a first high-side transistor coupled between an input voltage and a high-side tap, a second high-side transistor coupled between the high-side tap and an output tap, a first low-side transistor coupled between a low-side tap and ground, and a second low-side transistor coupled between the output tap and the low-side tap; a flying capacitor coupled between the high-side tap and the low-side tap; an inductor coupled between the output tap and an output node; an output capacitor coupled between the output node and ground; and a feedback divider coupled in parallel with the output capacitor, with a feedback voltage being formed at a tap of the feedback divider; a ramp generator configured to generate a first ramp signal and a second ramp signal, wherein the ramp generator generates the first ramp signal as a function of a constant reference voltage and generates the second ramp signal as a function of a difference between a voltage across the flying capacitor and one half the input voltage; control circuitry configured to: generate an error signal based on a comparison between the feedback voltage and a reference voltage; generate a first high-side control signal for the first high-side transistor, and a first low-side control signal for the first low-side transistor, based on a comparison between the first ramp signal and the error signal; and generate a second high-side control signal for the second high-side transistor, and a second low-side control signal for the second low-side transistor, based on a comparison between the second ramp signal and the error signal.
2. 22. The DC-DC converter of claim 1, wherein the ramp generator comprises: first ramp generation circuitry comprising: a first voltage-to-current converter configured to generate a first charging current based upon the constant reference voltage; a first timing capacitor configured to be charged by the first charging current; and a first reset transistor configured to discharge the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.
3. 33. The DC-DC converter of claim 2, wherein the first voltage-to-current converter comprises: a first amplifier having a non-inverting input receiving the constant reference voltage, an inverting input coupled to ground through a first sense resistor, and an output; a first n-channel transistor having a source coupled to ground through the first sense resistor, a gate coupled to the output of the first amplifier, and a drain; a first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the first n-channel transistor, and a gate coupled to the drain of the first p-channel transistor; a second p-channel transistor having a source coupled to the supply voltage, a drain coupled to the first timing capacitor, and a gate coupled to the gate of the first p-channel transistor; and a second n-channel transistor having a drain coupled to the first timing capacitor, a source coupled to ground, and a gate coupled to a first reset signal, assertion of the first reset signal corresponding to the first edge of the clock signal.

TECHNICAL FIELD
This disclosure is directed to the field of power electronics and, in particular, to control systems for three-level buck converters.
BACKGROUND
DC-DC converters are frequently utilized in modern electronic devices, providing the necessary voltage transformation for a variety of applications. Buck converters, in particular, are utilized for their efficiency in stepping down voltage.
Two-level buck converters are widely utilized in low to medium power applications. However, as power requirements increase, issues such as electromagnetic interference, switching losses, and the need for larger inductors and capacitors become more significant. To address these concerns, three-level buck converters have been developed and utilize additional switches and capacitors to create intermediate voltage levels. This design reduces the voltage stress on each switch, allowing for the use of lower-rated and more efficient components.
A known three-level buck converter 10 is now described with reference to FIG. 1. The three-level buck converter 10 includes: a first n-channel transistor MN1 having its drain connected to an input voltage VIN and its source connected to a first tap TAP1, a second n-channel transistor MN2 having its drain connected to the first tap TAP1 and its source connected to a second tap TAP2, a third n-channel transistor MN3 having its drain connected to the second tap TAP2 and its source connected to a third tap TAP3, and a fourth n-channel transistor MN4 having its drain connected to the third tap TAP3 and its source coupled to ground. The gates of n-channel transistors MN1, MN2, MN3, MN4 are driven by respective control voltages HS1, HS2, LS2, LS1 generated by a logic/driver circuit 15—assertion of control voltage HS1 turns on transistor MN1 while deassertion of HS1 control voltage turns off transistor MN1, assertion of control voltage HS2 turns on transistor MN2 while deassertion of control voltage HS2 turns off transistor MN2, assertion of control voltage LS2 turns on transistor MN3 while deassertion of control voltage LS2 turns off transistor MN3, and assertion of control voltage LS1 turns on transistor MN4 while deassertion of control voltage LS1 turns off transistor MN4.
A flying capacitor CFLY is connected between first tap TAP1 and third tap TAP3. An inductor L is connected between the second tap TAP2 and an output capacitor COUT at which an output voltage VOUT is produced. A feedback divider is formed by feedback resistors RFB1, RFB2 connected in series between the output capacitor COUT and ground, with a feedback voltage VFB being formed at the tap between resistors RFB1, RFB2.
A proportional-integral-derivative (PID) controller 14 receives the feedback voltage VFB and a reference voltage VREF as input and generates an error voltage VERROR based upon the difference between the feedback voltage VFB and the reference voltage VREF. A first comparator 11 receives the error voltage VERROR at its non-inverting input, compares it to a first ramp signal RAMP1 received at its inverting input from a ramp generator 13, and provides output OUT1 to the logic/driver circuit 15. A second comparator 12 receives the error voltage VERROR at its non-inverting input, compares it to a second ramp signal RAMP2 received at its inverting input from the ramp generator 13, and provides output OUT2 to the logic/driver circuit 15. The ramp signals RAMP1 and RAMP2 are 180° out of phase.
Operation with a duty cycle of less than 50%, where VOUT<VIN/2, includes three phases. In the first phase, control voltages HS1 and LS2 are asserted, resulting in current flow from VIN, through transistor MN1, through capacitor CFLY, and out to inductor L through transistor MN3. As shown in the graphs of FIGS. 2A-2B, during this first phase, assuming VCFLY=VIN/2, the voltage VLX formed at the second tap TAP2 is equal to one half the input voltage, namely VLX=VIN/2, and the inductor current increases with a rate of change of



 
  
   
    
     V
     
      IN
      /
      2
     
    
    -
    
     V
     OUT
    
   
   L
  
  .
 



In the second phase, control voltages LS1 and LS2 are asserted to turn on transistors MN3 and MN4, resulting in in discharge of the inductor L. As shown in the graphs of FIGS. 2A-2B, during this second phase, the voltage VLX is equal to 0 and the inductor current decreases with a rate of change of −VOUT/L. In the third phase, control voltages HS2 and LS1 are asserted to turn on transistors MN2 and MN4, resulting in discharge of the flying capacitor CFLY to inductor L. As shown in the graphs of FIGS. 2A-2B, during this third phase, the voltage VLX formed at second tap TAP2 is equal to one half the input voltage, namely VLX=VIN/2, and the inductor current increases with a rate of change of




 
  
   
    
     V
     
      IN
      /
      2
     
    
    -
    
     V
     OUT
    
   
   L
  
  .
 



As shown in FIG. 2C, the order of phase execution is Phase 1, Phase 2, Phase 3, Phase 2, Phase 1, Phase 2, Phase 3, Phase 2, etc.
Operation with a duty cycle of greater than 50%, where VOUT>VIN/2, includes the above described first and third phases, as well as a fourth phase. In the fourth phase, control voltages HS1 and HS2 are asserted, resulting in current flow from the input voltage VIN, through transistor MN1, through transistor MN2 to inductor L.
As shown in the graphs of FIGS. 3A-3B, during this fourth phase, the voltage VLX formed at second tap TAP2 is equal to the input voltage, namely VLX=VIN, and the inductor current increases with a rate of change of



 
  
   
    
     V
     IN
    
    -
    
     V
     OUT
    
   
   L
  
  .
 



During the first phase, the voltage VLX formed at the second tap TAP2 is VIN/2, and the inductor current decreases with a rate of change of




 
  
   
    
     V
     
      IN
      /
      2
     
    
    -
    
     V
     OUT
    
   
   L
  
  .
 



During the third phase, the voltage VLX formed at the second tap TAP2 is VIN/2 and the inductor current decreases with a rate of change of




 
  
   
    
     V
     
      IN
      /
      2
     
    
    -
    
     V
     OUT
    
   
   L
  
  .
 



As shown in FIG. 3C, the order of phase execution is Phase 4, Phase 1, Phase 4, Phase 3, Phase 4, Phase 1, Phase 4, Phase 3, etc.
An advantage of three-levels buck converters such as that of FIG. 1 is their capacity to employ power MOSFETs MN1, MN2, MN3, MN4 with an Absolute Maximum Rating (AMR) equivalent to VIN/2 assuming that the flying capacitor CFLY is maintained at a consistent voltage VCFLY level of VIN/2, This not only enhances the efficiency of the three-level converter but also allows for the utilization of lower-rated, and hence potentially more economical, power MOSFETs. Practical implementations incorporate a safety margin to account for dynamic variations and provide for the reliability of the three-level buck converter under fluctuating operating conditions. A deviation from the ideal condition, where the voltage across the flying capacitor CFLY does not equal VIN/2, can lead to suboptimal current waveforms through the inductor L, which may compromise the performance of the three-level buck converter.
Therefore, development of techniques to maintain the voltage across the flying capacitor CFLY at VIN/2 is needed.
SUMMARY
Disclosed herein is a DC-DC converter including a power stage, the power stage including: a first high-side transistor coupled between an input voltage and a high-side tap, a second high-side transistor coupled between the high-side tap and an output tap, a first low-side transistor coupled between a low-side tap and ground, and a second low-side transistor coupled between the output tap and the low-side tap; a flying capacitor coupled between the high-side tap and the low-side tap; an inductor coupled between the output tap and an output node; an output capacitor coupled between the output node and ground; and a feedback divider coupled in parallel with the output capacitor, with a feedback voltage being formed at a tap of the feedback divider. The DC-DC converter further includes a ramp generator configured to generate a first ramp signal and a second ramp signal, wherein the ramp generator generates the first ramp signal as a function of a constant reference voltage and generates the second ramp signal as a function of a difference between a voltage across the flying capacitor and one half the input voltage.
Control circuitry in the DC-DC converter is configured to: generate an error signal based on a comparison between the feedback voltage and a reference voltage; generate a first high-side control signal for the first high-side transistor, and a first low-side control signal for the first low-side transistor, based on a comparison between the first ramp signal and the error signal; and generate a second high-side control signal for the second high-side transistor, and a second low-side control signal for the second low-side transistor, based on a comparison between the second ramp signal and the error signal.
The ramp generator may be formed by first ramp generation circuitry which includes: a first voltage-to-current converter configured to generate a first charging current based upon the constant reference voltage; a first timing capacitor configured to receive the first charging current; and a first reset transistor configured to discharge the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.
The first voltage-to-current converter may include: a first amplifier having a non-inverting input receiving the constant reference voltage, an inverting input coupled to ground through a first sense resistor, and an output; a first n-channel transistor having a source coupled to ground through the first sense resistor, a gate coupled to the output of the first amplifier, and a drain; a first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the first n-channel transistor, and a gate coupled to the drain of the first p-channel transistor; a second p-channel transistor having a source coupled to the supply voltage, a drain coupled to the first timing capacitor, and a gate coupled to the gate of the first p-channel transistor; and a second n-channel transistor having a drain coupled to the first timing capacitor, a source coupled to ground, and a gate coupled to a first reset signal, assertion of the first reset signal corresponding to the first edge of the clock signal.
The ramp generator may also have second ramp generation circuitry which includes: a second voltage-to-current converter configured to generate a second charging current based upon the difference between the voltage across the flying capacitor and one half the input voltage; a second timing capacitor configured to receive the second charging current; and a second reset transistor configured to discharge the second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated as a function of the charging and discharging of the second timing capacitor.
The second voltage-to-current converter may include: a second amplifier having a non-inverting input receiving a delta voltage whose slope is proportional to the difference between one half the input voltage and the voltage across the flying capacitor, an inverting input coupled to ground through a second sense resistor, and an output; a third n-channel transistor having a source coupled to ground through the second sense resistor, a gate coupled to the output of the second amplifier, and a drain; a third p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the third n-channel transistor, and a gate coupled to the drain of the third p-channel transistor; a fourth p-channel transistor having a source coupled to the supply voltage, a drain coupled to the second timing capacitor, and a gate coupled to the gate of the third p-channel transistor; and a fourth n-channel transistor having a drain coupled to the second timing capacitor, a source coupled to ground, and a gate coupled to a second reset signal, assertion of the second reset signal corresponding to the second edge of the clock signal.
The DC-DC converter may include balancing circuitry, the balancing circuitry having an amplifier having a first input coupled to receive one half the input voltage, a second input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the second input through a balance capacitor, wherein a delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor. The second voltage-to-current converter generates the second charging current based upon the delta voltage.
The DC-DC converter may include balancing circuitry, the balancing circuitry having an amplifier having a non-inverting input coupled to receive one half the input voltage, an inverting input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the inverting input through a balance capacitor, wherein a delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor. The second voltage-to-current converter generates the second charging current based upon the delta voltage.
Method aspects are disclosed. For example, disclosed herein is a method of operating a DC-DC converter, including: converting an input voltage to an output voltage using a power stage; generating a first ramp signal as a function of a constant reference voltage; generating a second ramp signal as a function of a difference between one half the input voltage and a voltage across a flying capacitor of the power stage; generating an error signal based on a comparison between a reference voltage and a feedback voltage representative of the output voltage; generating a first high-side control signal for a first high-side transistor of the power stage, and a first low-side control signal for a first low-side transistor of the power stage, based on a comparison between the first ramp signal and the error signal; and generating a second high-side control signal for a second high-side transistor of the power stage, and a second low-side control signal for a second low-side transistor of the power stage, based on a comparison between the second ramp signal and the error signal.
Generating the first ramp signal may include: generating a first charging current based upon the constant reference voltage; receiving the first charging current at a first timing capacitor; and discharging the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.
Generating the second ramp signal may include: generating a second charging current based on a delta voltage whose slope is proportional to a difference between one half the input voltage and the voltage across the flying capacitor; receiving the second charging current at a second timing capacitor; and discharging the second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated as a function of the charging and discharging of the second timing capacitor.
Also disclosed herein is a DC-DC converter, including: a power stage configured to convert an input voltage to an output voltage using a power stage; and a ramp generator. The ramp generator is configured to: generate a first ramp signal as a function of a constant reference voltage; and generate a second ramp signal as a function of a difference between one half the input voltage and a voltage across a flying capacitor of the power stage. An error amplifier is configured to generate an error signal based on a comparison between a reference voltage and a feedback voltage representative of the output voltage. Control circuitry is configured to: generate a first high-side control signal for a first high-side transistor of the power stage, and a first low-side control signal for a first low-side transistor of the power stage, based on a comparison between the first ramp signal and the error signal; and generate a second high-side control signal for a second high-side transistor of the power stage, and a second low-side control signal for a second low-side transistor of the power stage, based on a comparison between the second ramp signal and the error signal.
The ramp generator may generate the first ramp signal by: generating a first charging current based upon the constant reference voltage; receiving the first charging current at a first timing capacitor; and discharging the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.
The ramp generator may generate the second ramp signal by: generating a second charging current based on a delta voltage whose slope is proportional to a difference between one half the input voltage and the voltage across the flying capacitor; receiving the second charging current at a second timing capacitor; and discharging the second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated as a function of the charging and discharging of the second timing capacitor.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram of a known three-level buck converter.
FIG. 2A is a graph of the inductor current of the three-level buck converter of FIG. 1 in operation when the duty cycle is less than 50%.
FIG. 2B is a graph of the voltage at the second tap node of the three-level buck converter of FIG. 1 in operation when the duty cycle is less than 50%.
FIG. 2C is a graph showing the ramp voltages, error signal, and gate control voltages of the three-level buck converter of FIG. 1 in operation when the duty cycle is less than 50%.
FIG. 3A is a graph of the inductor current of the three-level buck converter of FIG. 1 in operation when the duty cycle is greater than 50%.
FIG. 3B is a graph of the voltage at the second tap node of the three-level buck converter of FIG. 1 in operation when the duty cycle is greater than 50%.
FIG. 3C is a graph showing the ramp voltages, error signal, and gate control voltages of the three-level buck converter of FIG. 1 in operation when the duty cycle is greater than 50%.
FIG. 4 is a schematic block diagram of a ramp generator usable with the three-level buck converter of FIG. 1 to operate the three-level buck converter such that the voltage across the flying capacitor CFLY is maintained at VIN/2.
FIG. 5A is a graph of the ramp voltages and control signals of the three-level buck converter of FIG. 1 when utilizing the ramp generator of FIG. 4 in a condition where the voltage VCFLY across the flying capacitor CFLY is lower than VIN/2.
FIG. 5B is a graph of the ramp voltages and control signals of the three-level buck converter of FIG. 1 when utilizing the ramp generator of FIG. 4 in a condition where the voltage VCFLY across the flying capacitor CFLY is higher than VIN/2.



DETAILED DESCRIPTION
The following disclosure enables a person skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. It is not intended to limit this disclosure to the embodiments shown, but to accord it the widest scope consistent with the principles and features disclosed or suggested herein.
Note that in the following descriptions given either hereinabove or hereinbelow, any resistor or resistance mentioned is a discrete device, unless stated otherwise, and is not simply an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than a lead between those two points, and such resistor or resistance cannot be interpreted as a lead. Similarly, any capacitor or capacitance mentioned is a discrete device, unless stated otherwise, and is not a parasitic element, unless stated otherwise. Additionally, any inductor or inductance mentioned is a discrete device, unless stated otherwise, and is not a parasitic element, unless stated otherwise.
Described herein with initial reference to FIG. 4 is a ramp generator 13′ usable with a three-level buck converter 10′ that causes that three-level buck converter, or any suitable three-level buck converter, to maintain the voltage VCFLY across the flying capacitor CFLY at the desired value of VIN/2 The difference between the three-level buck converter 10′ of FIG. 4 and the three-level buck converter 10 of FIG. 1 is that the three-level buck converter 10′ of FIG. 4 includes ramp generator 13′ as opposed to ramp generator 13.
The ramp generator 13′ includes a first ramp generator circuit 16 for generating the first ramp signal RAMP1 and a second ramp generator circuit 17 for generating the second ramp signal RAMP2.
The first ramp generator circuit 16 includes an amplifier 21 having its non-inverting input coupled to receive a fixed ramp reference voltage VREF RAMP, its inverting input coupled to ground through a sense resistor RS1, and its output connected to the gate of n-channel transistor MN5. N-channel transistor MN5 has its source connected to the inverting input of the amplifier 21 and its drain connected to the drain and gate of p-channel transistor MP1. P-channel transistor MP1 has its source coupled to a supply voltage VCC and its drain connected to its gate and to the drain of n-channel transistor MN5. P-channel transistor MP2 has its source coupled to the supply voltage VCC, its drain coupled to ground through timing capacitor CS1, and its gate connected to the gate of p-channel transistor MP1. N-channel transistor MN6 has its drain connected to the drain of p-channel transistor MP2, its source coupled to ground, and its gate coupled to a first reset signal RESET1.
The second ramp generator circuit 17 includes an amplifier 22 having its non-inverting input coupled to receive a voltage DELTA whose slope is proportional to the difference between the desired voltage VIN/2 and the voltage VCFLY across the flying capacitor CFLY. The amplifier 22 has its inverting input coupled to ground through a sense resistor RS2, and its output connected to the gate of n-channel transistor MN7. N-channel transistor MN7 has its source connected to the inverting input of the amplifier 22 and its drain connected to the drain and gate of p-channel transistor MP3. P-channel transistor MP3 has its source coupled to the supply voltage VCC and its drain connected to its gate and to the drain of n-channel transistor MN7. P-channel transistor MP4 has its source coupled to the supply voltage VCC, its drain coupled to ground through timing capacitor CS2, and its gate connected to the gate of p-channel transistor MP3. N-channel transistor MN8 has its drain connected to the drain of p-channel transistor MP4, its source coupled to ground, and its gate coupled to a second reset signal RESET2.
The voltage DELTA is generated by balancing circuit 25. Balancing circuit 25 includes an amplifier 23 having its inverting input coupled to receive the voltage VCFLY through resistor RB, its non-inverting input coupled to receive the desired voltage VIN/2, and its output connected to the inverting input of amplifier 22 to provide DELTA thereto. A feedback capacitor CB is connected between the inverting input and the output of the amplifier 23.
The generation of the control voltages HS1, HS2, LS1, LS2 by the logic/driver circuitry 15 of FIG. 4 is now described. Comparator 11 receives the error voltage VERROR at its non-inverting input, receives the first ramp signal RAMP1 at its inverting input, and provides output to the logic/driver circuitry 15 which generates the control voltage HS1 based upon the comparison between VERROR and RAMP1, and generates control voltage LS1 as the inverse of control voltage HS1. Comparator 12 receives the error voltage VERROR at its non-inverting input, receives the second ramp signal RAMP2 at its inverting input, and provides output to the logic/driver circuitry 15 which generates the control voltage HS2 based upon the comparison between VERROR and RAMP2, and generates control voltage LS2 as the inverse of control voltage HS2.
In operation, the arrangement of the amplifier 21 and n-channel transistor MN5 acts as a voltage to current converter, with n-channel transistor MN5 sinking a current equal to VREFRAMP/RS1. The current sunk by n-channel transistor MN5 is mirrored by the current mirror arrangement of p-channel transistors MP1 and MP2 to produce a charging current ICHG. Beginning with deassertion of the reset signal RESET1 (which may occur at a rising or falling edge of a clock signal), the charging current ICHG1 charges timing capacitor CS1. Due to the aforementioned voltage to current converter arrangement, the charging current ICHG1 is equal to VREFRAMP/RS1, and charges the timing capacitor CS1 until the reset signal RESET is asserted at the next edge of the clock signal.
The peak voltage of the first ramp signal RAMP1 achieved during a cycle can be calculated as



 
  
   
    V
    
     PEAK
     ⁢
     1
    
   
   =
   
    
     
      
       T
       CLK
      
      
       
        R
        
         S
         ⁢
         1
        
       
       ·
       
        C
        
         S
         ⁢
         1
        
       
      
     
     ·
     
      V
      REF
     
    
    ⁢
    RAMP
   
  
  ,
 



where TCLK is the switching period of the clock signal (and thus the reset signal RESET1).

The arrangement of the amplifier 22 and n-channel transistor MN7 acts as a voltage to current converter, with n-channel transistor MN7 sinking a current equal to DELTA/RS2. The current sunk by n-channel transistor MN7 is mirrored by the current mirror arrangement of p-channel transistors MP3 and MP4 to produce a charging current ICHG2. Beginning with deassertion of the reset signal RESET2 (which may occur at a falling or rising edge of a clock signal, with RESET2 being the opposite of RESET1), the charging current ICHG2 charges timing capacitor CS2. The charging current ICHG2 is equal to DELTA/RS2, and charges the timing capacitor CS2 until the reset signal RESET2 is asserted at the next edge of the clock signal.
The peak voltage of the second ramp signal RAMP2 achieved during a cycle can be calculated as



 
  
   
    V
    
     PEAK
     ⁢
     2
    
   
   =
   
    
     
      
       T
       CLK
      
      
       
        R
        
         S
         ⁢
         2
        
       
       ·
       
        C
        
         S
         ⁢
         2
        
       
      
     
     ·
     DELTA
    
    -
   
  
  ,
 



where TCLK is the switching period of the clock signal (and thus the reset signal RESET2).

Appreciate from the above that the first ramp signal RAMP1 has a fixed amplitude because it is generated based upon the ramp reference voltage VREFRAMP, which is a fixed signal, while the second ramp signal RAMP2 has a variable amplitude that is proportional to DELTA. This generation of the second ramp signal RAMP2 to be proportional to DELTA, which itself has a slope proportional to the difference between the desired voltage VIN/2 and the voltage VCFLY across the flying capacitor CFLY provides for correction of mismatch between the first ramp signal RAMP1 and second ramp signal RAMP2 due to process, device variation, etc.
For example, if the voltage VCFLY across the flying capacitor CFLY is lower than VIN/2, DELTA will increase, and as a result the amplitude of ramp signal RAMP2 will be higher than that of RAMP1, having the effect of the pulse width of control voltages HS1, LS1 being wider than the pulse width of control voltages HS2, LS2. Thus, the charging phase of the first ramp generator circuit 16 will be longer than the discharging phase of the second ramp generator circuit 17, causing the voltage VCFLY across the flying capacitor CFLY to increase until it is equal to VIN/2.
Operation in this condition (in which the voltage VCFLY across the flying capacitor CFLY is lower than VIN/2) is shown in the graphs of FIG. 5A, where the above-described effects on control voltages HS2, LS2 and ramp signal RAMP2 can be observed.
Conversely, if the voltage VCFLY across the flying capacitor CFLY is higher than VIN/2, DELTA will decrease, and a result of this, the amplitude of ramp signal RAMP2 will be lower than that of ramp signal RAMP1, having the effect of the pulse width of control voltages HS2, LS2 being wider than the pulse width of control voltages HS1, LS1. Thus, the discharging phase of the second ramp generator circuit 17 will be longer than the charging phase of the first ramp generator circuit 16, causing the voltage VCFLY across the flying capacitor CFLY to decrease until it is equal to VIN/2.
Operation in this condition (in which the voltage VCFLY across the flying capacitor CFLY is higher than VIN/2) is shown in the graphs of FIG. 5B, where the above-described effects on control voltages HS2, LS2 and ramp signal RAMP2 can be observed.
When steady state is achieved, voltage DELTA will be substantially equal to the ramp reference voltage VREFRAMP except for mismatches between the two ramp generators 16 and 17.
The use of the ramp generator 13′ provides for maintenance of the voltage across the flying capacitor CFLY at VIN/2, which as explained above is desirable for efficiency reasons and for proper performance of the three-level buck converter.
It is evident that modifications and variations can be made to what has been described and illustrated herein without departing from the scope of this disclosure. For example, the ramp generator 13′ described herein is usable with other types of three-level DC-DC converters, for example three-level boost converters.
Although this disclosure has been described with a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, can envision other embodiments that do not deviate from the disclosed scope. Furthermore, skilled persons can envision embodiments that represent various combinations of the embodiments disclosed herein made in various ways.